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The Principle Of Latching Effect And The Method Of Avoiding It
- Jul 31, 2017 -

Latch up is 

most likely to occur at I / O circuits that are susceptible to external disturbances and occasionally in internal circuits. 


Latch up is 

the cmos wafer, between the power supply power VDD and the ground GND (VSS) due to parasitic PNP and NPN Bipolar BJT interacts with each other with a low impedance path, and its presence causes a high current between VDD and GND. 


As the IC manufacturing process evolves

the packaging density and integration are getting higher and higher, resulting in the possibility of Latch up Latch up is one of the most important measures of IC Layout. Latch up is one of the most important measures of IC Layout.

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